May 28, 2026 -- Skoltech (part of the VEB.RF group) has announced the start of applications for Russia’s first contract manufacturing run of photonic integrated circuits (PICs) on a silicon‑on‑insulator (SOI) platform. The announcement was made by Skoltech President, RAS Academician Yulia Gorbunova at the opening ceremony of the Microelectronic Systems 2026 (MES) conference, held at Skoltech on May 27-28.

The manufacturing run will be carried out in a multi‑project wafer (MPW) format — a production method in which circuits designed by different customers are fabricated simultaneously on a single wafer within one process cycle. This approach significantly reduces the final cost of PICs for each customer, since the costs of expensive manufacturing are shared evenly among all participants.

Through this service, Russian and international customers will receive prototypes and small batches of their silicon photonic chips fabricated using an industrial CMOS‑compatible process. Thanks to the advantages of the SOI platform — such as compactness and the ability to create functional elements including optical modulators — these chips will find applications in high‑speed optical communications, optical computing, artificial intelligence systems, sensing, and other rapidly growing industries.

For the first manufacturing run, customers will have access to a basic set of standard PIC elements included in the Process Design Kit (PDK) — verified and ready for use in designs. This PDK provides a standard “construction kit” for silicon photonics, enabling the development of modules for a wide range of applications.

Currently available elements include:

• Partially and fully etched waveguides with specific propagation losses of 2 ± 0.5 dB/cm;
• Edge couplers (UHNA fiber tapers) with losses of 7 dB ± 1 dB, and diffraction gratings with an 8° input/output angle and losses of 6 ± 1 dB;
• 1×2 and 2×2 multimode interference (MMI) couplers;
• Directional couplers with adjustable splitting ratio;
• Ring resonators with a Q‑factor of up to 10⁵ depending on configuration;
• Thermo‑optical modulators with switching frequency up to 10 kHz;
• Metal heaters made of refractory metal for tuning PIC elements, with a control voltage of 0–10 V.

Key parameters of the SOI service: silicon device layer thickness 220 ± 10 nm, wavelength range 1530‑1565 nm (C‑band), cell size up to 5×5 mm², minimum feature size 85 nm. Up to 100 photonic chips will be fabricated in the first run.

The PDK for the new contract manufacturing service is being developed jointly with Difra Lab LLC, the developer of Russia’s first software for PIC design and simulation. The work is supported by the Russian Science Foundation under a grant for applied research in priority areas of scientific and technological development of the Russian Federation, specifically in “Microelectronics.” The PDK includes parameterized library elements, schematic and system simulation models, complete design rules for the specific technology stack, and verified parametric models accounting for losses, dispersion, process variations, and other factors. This level of detail matches the practice of leading global MPW services, where the PDK is the key interface between design centers and manufacturing.

As with other MPW initiatives, Skoltech’s service provides full customer support: process documentation, reference designs, testing recommendations, and, if needed, consulting on adapting designs to the technology, as well as optoelectronic assembly of PIC dies into final device prototypes. This will enable PIC developers — from research labs and fabless companies to R&D centers of optoelectronic equipment manufacturers — to move faster from concept to working chips on a domestic SOI platform without the need to build and operate their own production lines.

Customer engagement will follow this process:

• Submit a free‑form application by email to photonicMPW@skoltech.ru no later than September 30, 2026;
• Sign a non‑disclosure agreement;
• Receive the PDK package (technology layers, design rules, element library, performance characteristics, models, etc.) and, if necessary, training on using the PDK and design environment;
• Provide the final GDS file of the project and specify order details (number of PIC dies required, need for basic testing and packaging);
• Sign the MPW run contract;
• Design Rule Check (DRC) and technology validation of the submitted files;
• Assemble designs from different customers into a common reticle on the wafer and transfer for production (tapeout);
• Complete the full SOI fabrication process;
• Perform electrical and optical testing if required;
• Dicing, polishing, and packaging of PIC dies;
• Deliver PIC dies to the customer with supporting documentation.

Estimated completion of the first batch of PIC dies: Q1 2027.

“In 2023–2024, Skoltech’s Research Facilities Center launched a unique rapid prototyping center for PIC‑based devices — in fact, the first center in Russia designed, built, and equipped specifically for integrated photonics. We have achieved a closed loop for creating optoelectronic devices: from design and wafer‑level fabrication to optoelectronic assembly and testing. The key feature of Skoltech’s new SOI service is that it uses an industrial CMOS‑compatible technology, not a research process, ensuring compatibility with industry requirements for reproducibility, reliability, and production volume. Since CMOS is the foundational technology of microelectronics, domestic microelectronics fabs will be able to adopt photonic technology with minimal overhead as demand grows. Skoltech’s technological roadmap foresees the development of high‑speed modulators with bandwidths of 20–30 GHz and beyond, which is critical for PICs for 400G/800G transceivers and next‑generation products,” said Alexey Denisov, Vice President for Research Infrastructure at Skoltech.
“In 2023–2024, Skoltech’s Research Facilities Center launched a unique rapid prototyping center for PIC‑based devices — in fact, the first center in Russia designed, built, and equipped specifically for integrated photonics. We have achieved a closed loop for creating optoelectronic devices: from design and wafer‑level fabrication to optoelectronic assembly and testing. The key feature of Skoltech’s new SOI service is that it uses an industrial CMOS‑compatible technology, not a research process, ensuring compatibility with industry requirements for reproducibility, reliability, and production volume. Since CMOS is the foundational technology of microelectronics, domestic microelectronics fabs will be able to adopt photonic technology with minimal overhead as demand grows. Skoltech’s technological roadmap foresees the development of high‑speed modulators with bandwidths of 20–30 GHz and beyond, which is critical for PICs for 400G/800G transceivers and next‑generation products,” said Alexey Denisov, Vice President for Research Infrastructure at Skoltech.